main Project Status (09/23/2011 - 12:27:58)
Project File: glitch48nofullpost.xise Parser Errors: No Errors
Module Name: main Implementation State: Fitted
Target Device: xc2c64a-7VQ44
  • Errors:
 No Errors
Product Version:ISE 12.2
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentven. 23. sept. 12:26:25 2011000
Translation ReportCurrentven. 23. sept. 12:27:49 2011000
CPLD Fitter Report (Text)Currentven. 23. sept. 12:27:53 201101 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datedim. 11. sept. 11:24:58 2011
Post-Fit Simulation Model Report  

Date Generated: 09/23/2011 - 12:27:58