The Development of the MU5 Computer System

Following a brief outline of the background
of the MU5 project, the aims and ideas for MU5 
are discussed.  A description is then given of the instruction
set, which includes a number of features 
conducive to the production of efficient compiled code
from high-level language source programs.  The 
design of the processor is then traced from the initial
ideas for an associatively addressed "name store" 
to the final multistage pipeline structure involving
a prediction mechanism for instruction prefetching 
and a function queue for array element accessing.  An
overall view of the complete MU5 complex is presented 
together with a brief indication of its performance.

CACM January, 1978

Ibbett, R.
Capon, P.

architecture, naming, virtual storage, instruction
set, descriptor, pipeline, instruction buffering, 
associative storage, function queue, computer complex

4.10 4.12 6.21 6.33

CA780103 JB March 28, 1978  5:44 PM

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