Empirical Evaluation of Some Features of Instruction Set Processor Architectures This paper presents methods for empirical evaluation of features of Instruction Set Processors (ISPs). ISP features are evaluated in terms of the time used or saved by having or not having the feature. The methods are based on analysis of traces of program executions. The concept of a register life is in troduced, and used to answer questions like: How many registers are used simultaneously? How many would be sufficient all of the time? Most of the time? What would the overhead be if the number of registers were reduced? What are registers used for during their lives? The paper also discusses the problem of detecting desirable but non-existing instructions. Other problems are briefly discussed. Experimental results are presented, obtained by analyzing 41 programs running on the DEC system 10 ISP. CACM March, 1977 Lunde, A. computer architecture, program behavior, instruction sets, op code utilization, register structures, register utilization, simultaneous register lives, instruction tracing, execution time 6.20 6.21 6.33 CA770303 JB December 30, 1977 1:00 AM 1653 4 2989 2411 4 2989 2709 4 2989 2889 4 2989 2937 4 2989 2989 4 2989 2989 4 2989 3005 4 2989 3025 4 2989 3101 4 2989 1069 5 2989 2138 5 2989 2989 5 2989 2989 5 2989 2989 5 2989 3025 5 2989 2138 6 2989 2989 6 2989