GBDK 2020 Docs 4.4.0 API Documentation for GBDK 2020

hardware.h
Go to the documentation of this file.
1
7 #ifndef _HARDWARE_H
8 #define _HARDWARE_H
9
10 #include <types.h>
11
12 #define __BYTES extern UBYTE
13 #define __BYTE_REG extern volatile UBYTE
14 #define __REG extern volatile SFR
15
18 __BYTES _VRAM[];
19 __BYTES _VRAM8000[];
20 __BYTES _VRAM8800[];
21 __BYTES _VRAM9000[];
22 __BYTES _SCRN0[];
23 __BYTES _SCRN1[];
24 __BYTES _SRAM[];
25 __BYTES _RAM[];
26 __BYTES _RAMBANK[];
27 __BYTES _OAMRAM[];
28 __BYTE_REG _IO[];
29 __BYTE_REG _AUD3WAVERAM[];
30 __BYTE_REG _HRAM[];
31
34 __BYTE_REG rRAMG;
35 __BYTE_REG rROMB0;
36 __BYTE_REG rROMB1;
37 __BYTE_REG rRAMB;
38
41 __BYTE_REG rMBC7_SRAM_ENABLE_1;
42 __BYTE_REG rMBC7_SRAM_ENABLE_2;
43 __BYTE_REG rMBC7_LATCH_1;
44 __BYTE_REG rMBC7_LATCH_2;
45 __BYTE_REG rMBC7_ACCEL_X_LO;
46 __BYTE_REG rMBC7_ACCEL_X_HI;
47 __BYTE_REG rMBC7_ACCEL_Y_LO;
48 __BYTE_REG rMBC7_ACCEL_Y_HI;
49
50 #define MBC7_LATCH_ERASE 0x55u
51 #define MBC7_LATCH_CAPTURE 0xAAu
52 #define MBC7_SRAM_ENABLE_KEY_1 0x0Au
53 #define MBC7_SRAM_ENABLE_KEY_2 0x40u
54
57 __REG P1_REG;
58 #define rP1 P1_REG
59
60 #define P1F_5 0b00100000
61 #define P1F_4 0b00010000
62 #define P1F_3 0b00001000
63 #define P1F_2 0b00000100
64 #define P1F_1 0b00000010
65 #define P1F_0 0b00000001
66
67 #define P1F_GET_DPAD P1F_5
68 #define P1F_GET_BTN P1F_4
69 #define P1F_GET_NONE (P1F_4 | P1F_5)
70
71 __REG SB_REG;
72 #define rSB SB_REG
73 __REG SC_REG;
74 #define rSC SC_REG
75
76 #define SIOF_XFER_START 0b10000000
77 #define SIOF_CLOCK_INT 0b00000001
78 #define SIOF_CLOCK_EXT 0b00000000
79 #define SIOF_SPEED_1X 0b00000000
80 #define SIOF_SPEED_32X 0b00000010
81 #define SIOF_B_CLOCK 0
82 #define SIOF_B_SPEED 1
83 #define SIOF_B_XFER_START 7
84 #define SCF_START SIOF_XFER_START
85 #define SCF_SOURCE SIOF_CLOCK_INT
86 #define SCF_SPEED SIOF_SPEED_32X
87
88 __REG DIV_REG;
89 #define rDIV DIV_REG
90 __REG TIMA_REG;
91 #define rTIMA TIMA_REG
92 __REG TMA_REG;
93 #define rTMA TMA_REG
94 __REG TAC_REG;
95 #define rTAC TAC_REG
96
97 #define TACF_START 0b00000100
98 #define TACF_STOP 0b00000000
99 #define TACF_4KHZ 0b00000000
100 #define TACF_16KHZ 0b00000011
101 #define TACF_65KHZ 0b00000010
102 #define TACF_262KHZ 0b00000001
103
104 __REG IF_REG;
105 #define rIF IF_REG
106
107 __REG NR10_REG;
108 #define rAUD1SWEEP NR10_REG
109 #define AUD1SWEEP_UP 0b00000000
110 #define AUD1SWEEP_DOWN 0b00001000
111 #define AUD1SWEEP_TIME(x) ((x) << 4)
112 #define AUD1SWEEP_LENGTH(x) (x)
113 __REG NR11_REG;
114 #define rAUD1LEN NR11_REG
115 __REG NR12_REG;
116 #define rAUD1ENV NR12_REG
117 __REG NR13_REG;
118 #define rAUD1LOW NR13_REG
119 __REG NR14_REG;
120 #define rAUD1HIGH NR14_REG
122 __REG NR21_REG;
123 #define rAUD2LEN NR21_REG
124 __REG NR22_REG;
125 #define rAUD2ENV NR22_REG
126 __REG NR23_REG;
127 #define rAUD2LOW NR23_REG
128 __REG NR24_REG;
129 #define rAUD2HIGH NR24_REG
131 __REG NR30_REG;
132 #define rAUD3ENA NR30_REG
133 __REG NR31_REG;
134 #define rAUD3LEN NR31_REG
135 __REG NR32_REG;
136 #define rAUD3LEVEL NR32_REG
137 __REG NR33_REG;
138 #define rAUD3LOW NR33_REG
139 __REG NR34_REG;
140 #define rAUD3HIGH NR34_REG
142 __REG NR41_REG;
143 #define rAUD4LEN NR41_REG
144 __REG NR42_REG;
145 #define rAUD4ENV NR42_REG
146 __REG NR43_REG;
147 #define rAUD4POLY NR43_REG
148 #define AUD4POLY_WIDTH_15BIT 0x00
149 #define AUD4POLY_WIDTH_7BIT 0x08
150 __REG NR44_REG;
151 #define rAUD4GO NR44_REG
153 __REG NR50_REG;
154 #define rAUDVOL NR50_REG
156 #define AUDVOL_VOL_LEFT(x) ((x) << 4)
157 #define AUDVOL_VOL_RIGHT(x) ((x))
158 #define AUDVOL_VIN_LEFT 0b10000000
159 #define AUDVOL_VIN_RIGHT 0b00001000
161 __REG NR51_REG;
162 #define rAUDTERM NR51_REG
164 #define AUDTERM_4_LEFT 0b10000000
165 #define AUDTERM_3_LEFT 0b01000000
166 #define AUDTERM_2_LEFT 0b00100000
167 #define AUDTERM_1_LEFT 0b00010000
168 #define AUDTERM_4_RIGHT 0b00001000
169 #define AUDTERM_3_RIGHT 0b00000100
170 #define AUDTERM_2_RIGHT 0b00000010
171 #define AUDTERM_1_RIGHT 0b00000001
173 __REG NR52_REG;
174 #define rAUDENA NR52_REG
176 #define AUDENA_ON 0b10000000
177 #define AUDENA_OFF 0b00000000
179 __BYTE_REG AUD3WAVE[16];
180 __BYTE_REG PCM_SAMPLE[16];
181
182 __REG LCDC_REG;
183 #define rLCDC LCDC_REG
184
185 #if defined(__TARGET_ap)
186 #define LCDCF_OFF 0b00000000
187 #define LCDCF_ON 0b00000001
188 #define LCDCF_WIN9800 0b00000000
189 #define LCDCF_WIN9C00 0b00000010
190 #define LCDCF_WINOFF 0b00000000
191 #define LCDCF_WINON 0b00000100
192 #define LCDCF_BG8800 0b00000000
193 #define LCDCF_BG8000 0b00001000
194 #define LCDCF_BG9800 0b00000000
195 #define LCDCF_BG9C00 0b00010000
196 #define LCDCF_OBJ8 0b00000000
197 #define LCDCF_OBJ16 0b00100000
198 #define LCDCF_OBJOFF 0b00000000
199 #define LCDCF_OBJON 0b01000000
200 #define LCDCF_BGOFF 0b00000000
201 #define LCDCF_BGON 0b10000000
202 #define LCDCF_B_ON 0
203 #define LCDCF_B_WIN9C00 1
204 #define LCDCF_B_WINON 2
205 #define LCDCF_B_BG8000 3
206 #define LCDCF_B_BG9C00 4
207 #define LCDCF_B_OBJ16 5
208 #define LCDCF_B_OBJON 6
209 #define LCDCF_B_BGON 7
210 #elif defined(__TARGET_duck)
211 #define LCDCF_OFF 0b00000000
212 #define LCDCF_ON 0b10000000
213 #define LCDCF_WIN9800 0b00000000
214 #define LCDCF_WIN9C00 0b00001000
215 #define LCDCF_WINOFF 0b00000000
216 #define LCDCF_WINON 0b00100000
217 #define LCDCF_BG8800 0b00000000
218 #define LCDCF_BG8000 0b00010000
219 #define LCDCF_BG9800 0b00000000
220 #define LCDCF_BG9C00 0b00000100
221 #define LCDCF_OBJ8 0b00000000
222 #define LCDCF_OBJ16 0b00000010
223 #define LCDCF_OBJOFF 0b00000000
224 #define LCDCF_OBJON 0b00000001
225 #define LCDCF_BGOFF 0b00000000
226 #define LCDCF_BGON 0b01000000
227 #define LCDCF_B_ON 7
228 #define LCDCF_B_WIN9C00 3
229 #define LCDCF_B_WINON 5
230 #define LCDCF_B_BG8000 4
231 #define LCDCF_B_BG9C00 2
232 #define LCDCF_B_OBJ16 1
233 #define LCDCF_B_OBJON 0
234 #define LCDCF_B_BGON 6
235 #else
236 #define LCDCF_OFF 0b00000000
237 #define LCDCF_ON 0b10000000
238 #define LCDCF_WIN9800 0b00000000
239 #define LCDCF_WIN9C00 0b01000000
240 #define LCDCF_WINOFF 0b00000000
241 #define LCDCF_WINON 0b00100000
242 #define LCDCF_BG8800 0b00000000
243 #define LCDCF_BG8000 0b00010000
244 #define LCDCF_BG9800 0b00000000
245 #define LCDCF_BG9C00 0b00001000
246 #define LCDCF_OBJ8 0b00000000
247 #define LCDCF_OBJ16 0b00000100
248 #define LCDCF_OBJOFF 0b00000000
249 #define LCDCF_OBJON 0b00000010
250 #define LCDCF_BGOFF 0b00000000
251 #define LCDCF_BGON 0b00000001
252 #define LCDCF_B_ON 7
253 #define LCDCF_B_WIN9C00 6
254 #define LCDCF_B_WINON 5
255 #define LCDCF_B_BG8000 4
256 #define LCDCF_B_BG9C00 3
257 #define LCDCF_B_OBJ16 2
258 #define LCDCF_B_OBJON 1
259 #define LCDCF_B_BGON 0
260 #endif
261
262 __REG STAT_REG;
263 #define rSTAT STAT_REG
264
265 #if defined(__TARGET_ap)
266 #define STATF_LYC 0b00000010
267 #define STATF_MODE10 0b00000100
268 #define STATF_MODE01 0b00001000
269 #define STATF_MODE00 0b00010000
270 #define STATF_LYCF 0b00100000
271 #define STATF_HBL 0b00000000
272 #define STATF_VBL 0b10000000
273 #define STATF_OAM 0b01000000
274 #define STATF_LCD 0b11000000
275 #define STATF_BUSY 0b01000000
276 #define STATF_B_LYC 1
277 #define STATF_B_MODE10 2
278 #define STATF_B_MODE01 3
279 #define STATF_B_MODE00 4
280 #define STATF_B_LYCF 5
281 #define STATF_B_VBL 7
282 #define STATF_B_OAM 6
283 #define STATF_B_BUSY 6
284 #else
285 #define STATF_LYC 0b01000000
286 #define STATF_MODE10 0b00100000
287 #define STATF_MODE01 0b00010000
288 #define STATF_MODE00 0b00001000
289 #define STATF_LYCF 0b00000100
290 #define STATF_HBL 0b00000000
291 #define STATF_VBL 0b00000001
292 #define STATF_OAM 0b00000010
293 #define STATF_LCD 0b00000011
294 #define STATF_BUSY 0b00000010
295 #define STATF_B_LYC 6
296 #define STATF_B_MODE10 5
297 #define STATF_B_MODE01 4
298 #define STATF_B_MODE00 3
299 #define STATF_B_LYCF 2
300 #define STATF_B_VBL 0
301 #define STATF_B_OAM 1
302 #define STATF_B_BUSY 1
303 #endif
304
305 __REG SCY_REG;
306 #define rSCY
307 __REG SCX_REG;
308 #define rSCX SCX_REG
309 __REG LY_REG;
310 #define rLY LY_REG
311 __REG LYC_REG;
312 #define rLYC LYC_REG
313 __REG DMA_REG;
314 #define rDMA DMA_REG
315 __REG BGP_REG;
316 #define rBGP BGP_REG
317 __REG OBP0_REG;
318 #define rOBP0 OBP0_REG
319 __REG OBP1_REG;
320 #define rOBP1 OBP1_REG
321 __REG WY_REG;
322 #define rWY WY_REG
323 __REG WX_REG;
324 #define rWX WX_REG
325 __REG KEY1_REG;
326 #define rKEY1 KEY1_REG
327 #define rSPD KEY1_REG
328
329 #define KEY1F_DBLSPEED 0b10000000
330 #define KEY1F_PREPARE 0b00000001
331
332 __REG VBK_REG;
333 #define rVBK VBK_REG
334
335 #define VBK_BANK_0 0
336 #define VBK_TILES 0
337 #define VBK_BANK_1 1
338 #define VBK_ATTRIBUTES 1
340 #define BKGF_PRI 0b10000000
341 #define BKGF_YFLIP 0b01000000
342 #define BKGF_XFLIP 0b00100000
343 #define BKGF_BANK0 0b00000000
344 #define BKGF_BANK1 0b00001000
346 #define BKGF_CGB_PAL0 0b00000000
347 #define BKGF_CGB_PAL1 0b00000001
348 #define BKGF_CGB_PAL2 0b00000010
349 #define BKGF_CGB_PAL3 0b00000011
350 #define BKGF_CGB_PAL4 0b00000100
351 #define BKGF_CGB_PAL5 0b00000101
352 #define BKGF_CGB_PAL6 0b00000110
353 #define BKGF_CGB_PAL7 0b00000111
355 __REG HDMA1_REG;
356 #define rHDMA1 HDMA1_REG
357 __REG HDMA2_REG;
358 #define rHDMA2 HDMA2_REG
359 __REG HDMA3_REG;
360 #define rHDMA3 HDMA3_REG
361 __REG HDMA4_REG;
362 #define rHDMA4 HDMA4_REG
363 __REG HDMA5_REG;
364 #define rHDMA5 HDMA5_REG
365
366 #define HDMA5F_MODE_GP 0b00000000
367 #define HDMA5F_MODE_HBL 0b10000000
368
369 #define HDMA5F_BUSY 0b10000000
370
371 __REG RP_REG;
372 #define rRP RP_REG
373
374 #define RPF_ENREAD 0b11000000
375 #define RPF_DATAIN 0b00000010
376 #define RPF_WRITE_HI 0b00000001
377 #define RPF_WRITE_LO 0b00000000
378
379 __REG BCPS_REG;
380 #define rBCPS BCPS_REG
381
382 #define BCPSF_AUTOINC 0b10000000
383 __REG BCPD_REG;
384 #define rBCPD BCPD_REG
385
386 __REG OCPS_REG;
387 #define rOCPS OCPS_REG
388
389 #define OCPSF_AUTOINC 0b10000000
390 __REG OCPD_REG;
391 #define rOCPD OCPD_REG
392 __REG SVBK_REG;
393 #define rSVBK SVBK_REG
394 #define rSMBK SVBK_REG
395
396 __REG PCM12_REG;
397 #define rPCM12 PCM12_REG
398
399 __REG PCM34_REG;
400 #define rPCM34 PCM34_REG
401
402 __REG IE_REG;
403 #define rIE IE_REG
404
405 #define IEF_HILO 0b00010000
406 #define IEF_SERIAL 0b00001000
407 #define IEF_TIMER 0b00000100
408 #define IEF_STAT 0b00000010
409 #define IEF_VBLANK 0b00000001
412 /* Square wave duty cycle */
413 #define AUDLEN_DUTY_12_5 0b00000000
414 #define AUDLEN_DUTY_25 0b01000000
415 #define AUDLEN_DUTY_50 0b10000000
416 #define AUDLEN_DUTY_75 0b11000000
417 #define AUDLEN_LENGTH(x) (x)
418
419 /* Audio envelope flags */
420 #define AUDENV_VOL(x) ((x) << 4)
421 #define AUDENV_UP 0b00001000
422 #define AUDENV_DOWN 0b00000000
423 #define AUDENV_LENGTH(x) (x)
424
425 /* Audio trigger flags */
426 #define AUDHIGH_RESTART 0b10000000
427 #define AUDHIGH_LENGTH_ON 0b01000000
428 #define AUDHIGH_LENGTH_OFF 0b00000000
429
430 /* OAM attributes flags */
431 #define OAMF_PRI 0b10000000
432 #define OAMF_YFLIP 0b01000000
433 #define OAMF_XFLIP 0b00100000
434 #define OAMF_PAL0 0b00000000
435 #define OAMF_PAL1 0b00010000
436 #define OAMF_BANK0 0b00000000
437 #define OAMF_BANK1 0b00001000
439 #define OAMF_CGB_PAL0 0b00000000
440 #define OAMF_CGB_PAL1 0b00000001
441 #define OAMF_CGB_PAL2 0b00000010
442 #define OAMF_CGB_PAL3 0b00000011
443 #define OAMF_CGB_PAL4 0b00000100
444 #define OAMF_CGB_PAL5 0b00000101
445 #define OAMF_CGB_PAL6 0b00000110
446 #define OAMF_CGB_PAL7 0b00000111
448 #define OAMF_PALMASK 0b00000111
450 #define DEVICE_SCREEN_X_OFFSET 0
451 #define DEVICE_SCREEN_Y_OFFSET 0
452 #define DEVICE_SCREEN_WIDTH 20
453 #define DEVICE_SCREEN_HEIGHT 18
454 #define DEVICE_SCREEN_BUFFER_WIDTH 32
455 #define DEVICE_SCREEN_BUFFER_HEIGHT 32
456 #define DEVICE_SCREEN_MAP_ENTRY_SIZE 1
457 #define DEVICE_SPRITE_PX_OFFSET_X 8
458 #define DEVICE_SPRITE_PX_OFFSET_Y 16
459 #define DEVICE_WINDOW_PX_OFFSET_X 7
460 #define DEVICE_WINDOW_PX_OFFSET_Y 0
461 #define DEVICE_SCREEN_PX_WIDTH (DEVICE_SCREEN_WIDTH * 8)
462 #define DEVICE_SCREEN_PX_HEIGHT (DEVICE_SCREEN_HEIGHT * 8)
464 #endif
rROMB1
__BYTE_REG rROMB1
Definition: hardware.h:36
NR33_REG
__REG NR33_REG
Definition: hardware.h:137
NR14_REG
__REG NR14_REG
Definition: hardware.h:119
P1_REG
__REG P1_REG
Definition: hardware.h:57
_SRAM
__BYTES _SRAM[]
Definition: hardware.h:24
__REG
#define __REG
Definition: hardware.h:14
rMBC7_SRAM_ENABLE_2
__BYTE_REG rMBC7_SRAM_ENABLE_2
Definition: hardware.h:42
SC_REG
__REG SC_REG
Definition: hardware.h:73
_IO
__BYTE_REG _IO[]
Definition: hardware.h:28
OBP0_REG
__REG OBP0_REG
Definition: hardware.h:317
HDMA5_REG
__REG HDMA5_REG
Definition: hardware.h:363
OCPS_REG
__REG OCPS_REG
Definition: hardware.h:386
rMBC7_ACCEL_Y_LO
__BYTE_REG rMBC7_ACCEL_Y_LO
Definition: hardware.h:47
WY_REG
__REG WY_REG
Definition: hardware.h:321
rMBC7_ACCEL_Y_HI
__BYTE_REG rMBC7_ACCEL_Y_HI
Definition: hardware.h:48
BCPD_REG
__REG BCPD_REG
Definition: hardware.h:383
SCY_REG
__REG SCY_REG
Definition: hardware.h:305
NR32_REG
__REG NR32_REG
Definition: hardware.h:135
PCM_SAMPLE
__BYTE_REG PCM_SAMPLE[16]
Definition: hardware.h:180
BCPS_REG
__REG BCPS_REG
Definition: hardware.h:379
_RAMBANK
__BYTES _RAMBANK[]
Definition: hardware.h:26
AUD3WAVE
__BYTE_REG AUD3WAVE[16]
Definition: hardware.h:179
WX_REG
__REG WX_REG
Definition: hardware.h:323
rMBC7_ACCEL_X_HI
__BYTE_REG rMBC7_ACCEL_X_HI
Definition: hardware.h:46
TMA_REG
__REG TMA_REG
Definition: hardware.h:92
HDMA4_REG
__REG HDMA4_REG
Definition: hardware.h:361
__BYTE_REG
#define __BYTE_REG
Definition: hardware.h:13
NR13_REG
__REG NR13_REG
Definition: hardware.h:117
PCM12_REG
__REG PCM12_REG
Definition: hardware.h:396
_HRAM
__BYTE_REG _HRAM[]
Definition: hardware.h:30
IF_REG
__REG IF_REG
Definition: hardware.h:104
NR43_REG
__REG NR43_REG
Definition: hardware.h:146
NR41_REG
__REG NR41_REG
Definition: hardware.h:142
HDMA3_REG
__REG HDMA3_REG
Definition: hardware.h:359
LYC_REG
__REG LYC_REG
Definition: hardware.h:311
VBK_REG
__REG VBK_REG
Definition: hardware.h:332
SB_REG
__REG SB_REG
Definition: hardware.h:71
rRAMG
__BYTE_REG rRAMG
Definition: hardware.h:34
LCDC_REG
__REG LCDC_REG
Definition: hardware.h:182
TAC_REG
__REG TAC_REG
Definition: hardware.h:94
NR24_REG
__REG NR24_REG
Definition: hardware.h:128
_VRAM9000
__BYTES _VRAM9000[]
Definition: hardware.h:21
NR21_REG
__REG NR21_REG
Definition: hardware.h:122
_OAMRAM
__BYTES _OAMRAM[]
Definition: hardware.h:27
_AUD3WAVERAM
__BYTE_REG _AUD3WAVERAM[]
Definition: hardware.h:29
KEY1_REG
__REG KEY1_REG
Definition: hardware.h:325
rMBC7_SRAM_ENABLE_1
__BYTE_REG rMBC7_SRAM_ENABLE_1
Definition: hardware.h:41
_VRAM8000
__BYTES _VRAM8000[]
Definition: hardware.h:19
RP_REG
__REG RP_REG
Definition: hardware.h:371
NR12_REG
__REG NR12_REG
Definition: hardware.h:115
NR23_REG
__REG NR23_REG
Definition: hardware.h:126
HDMA2_REG
__REG HDMA2_REG
Definition: hardware.h:357
NR44_REG
__REG NR44_REG
Definition: hardware.h:150
NR30_REG
__REG NR30_REG
Definition: hardware.h:131
SCX_REG
__REG SCX_REG
Definition: hardware.h:307
NR50_REG
__REG NR50_REG
Definition: hardware.h:153
TIMA_REG
__REG TIMA_REG
Definition: hardware.h:90
OBP1_REG
__REG OBP1_REG
Definition: hardware.h:319
rMBC7_ACCEL_X_LO
__BYTE_REG rMBC7_ACCEL_X_LO
Definition: hardware.h:45
SVBK_REG
__REG SVBK_REG
Definition: hardware.h:392
IE_REG
__REG IE_REG
Definition: hardware.h:402
HDMA1_REG
__REG HDMA1_REG
Definition: hardware.h:355
__BYTES
#define __BYTES
Definition: hardware.h:12
NR51_REG
__REG NR51_REG
Definition: hardware.h:161
NR34_REG
__REG NR34_REG
Definition: hardware.h:139
NR42_REG
__REG NR42_REG
Definition: hardware.h:144
rMBC7_LATCH_2
__BYTE_REG rMBC7_LATCH_2
Definition: hardware.h:44
_RAM
__BYTES _RAM[]
Definition: hardware.h:25
rRAMB
__BYTE_REG rRAMB
Definition: hardware.h:37
NR52_REG
__REG NR52_REG
Definition: hardware.h:173
_SCRN0
__BYTES _SCRN0[]
Definition: hardware.h:22
PCM34_REG
__REG PCM34_REG
Definition: hardware.h:399
STAT_REG
__REG STAT_REG
Definition: hardware.h:262
NR11_REG
__REG NR11_REG
Definition: hardware.h:113
NR10_REG
__REG NR10_REG
Definition: hardware.h:107
rROMB0
__BYTE_REG rROMB0
Definition: hardware.h:35
DMA_REG
__REG DMA_REG
Definition: hardware.h:313
OCPD_REG
__REG OCPD_REG
Definition: hardware.h:390
NR31_REG
__REG NR31_REG
Definition: hardware.h:133
_VRAM
__BYTES _VRAM[]
Definition: hardware.h:18
LY_REG
__REG LY_REG
Definition: hardware.h:309
rMBC7_LATCH_1
__BYTE_REG rMBC7_LATCH_1
Definition: hardware.h:43
NR22_REG
__REG NR22_REG
Definition: hardware.h:124
BGP_REG
__REG BGP_REG
Definition: hardware.h:315
_VRAM8800
__BYTES _VRAM8800[]
Definition: hardware.h:20
DIV_REG
__REG DIV_REG
Definition: hardware.h:88
_SCRN1
__BYTES _SCRN1[]
Definition: hardware.h:23