SystemVerilog 3.1.0 Changelog:

## Improvement ##
  - Alignement:
    * New option sv.align_paren to enable/disable alignement of closing parenthesis in instance
    * Fix mis-alignement in port declaration when using the var keyword
  - Popup :
    * Add link to struct/enum definition
    * Fix case of one letter class definition for static field access
  - Navigation:
    * Goto Declaration now works on field
    * Better handling of unsave file
