SystemVerilog 2.15.7 Changelog:

## Fix ###
 - Completion:
    * modport won't appear twice in the completion
    * clocking block are now properly tagged as such and put after the signal list
 - Parsing:
    * Now recognize function with old-style defintion of input parameters
 - Snippets: fix bad indentation in the class snippets
 - Module instance: fix regression where no module was found
