Project Settings
Project Name ice40blinkingled_syn Implementation Name ice40blinkingled_Implmnt
Top Module [auto] Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 0 0 - 0m:02s - 18-Jul-16
9:40:37 AM
(premap)Complete 3 0 0 0m:00s 0m:00s 79MB 18-Jul-16
9:40:44 AM
(fpga_mapper)Complete 12 0 0 0m:01s 0m:01s 80MB 18-Jul-16
9:40:47 AM
Multi-srs Generator Complete0m:01s18-Jul-16
9:40:40 AM

Area Summary
PADS 5 FLOPS 49
RAMS (v_ram) 0 CARRYS 46
LUTS (total_luts) 70

Timing Summary
Clock NameReq FreqEst FreqSlack
CLK100.0 MHz101.6 MHz0.158

Optimizations Summary
Combined Clock Conversion 1 / 0